a. Field of the Invention
The present invention relates to a phase matching circuit for receiving first data synchronized with a first clock and outputting second data of the same content as the first data synchronized with a second clock which has the same frequency as the first clock, and more particularly to a phase matching circuit suitable for changing the clock from the receiving clock to a system clock at a terminal repeater in a synchronous multiplex transmission system for transmitting a signal having used and unused data regions.
b. Description of the Related Art
In an apparatus for high speed transmission of signals which multiplex a voice signal and an image signal, the transmitter and receiver are operated synchronously. In this case, a phase matching circuit is provided within a terminal repeater connecting respective units in order to match the phase of the clocks of the respective units for the purpose of changing the clocks in the adequate timing during transfer of clocks between the units. However, although the prior art includes such a phase matching circuit, it has generated a problem in that accurate processing cannot be carried out in the receiving apparatus because valid data which are read in the receiving side apparatus are missed or such valid data are read twice due to the matching of the clocks using the phase matching circuit associated with the prior art.
An example of the structure of a known phase matching circuit is shown in FIG. 1. CK1 denotes a first clock used in the transmitting side apparatus, while D1 denotes first data output from the transmitting side apparatus. CK2 denotes a second clock used in the receiving side apparatus, while D2 denotes second data input to the receiving side apparatus. The first data D1 and second data D2 have the same content, and the first clock and second clock have the same frequency.
Reference numeral 101 denotes an input buffer which takes the first data D1 from the transmitting apparatus in accordance with the first clock CK1 used in the transmitting apparatus, 102 denotes an output buffer which sends the second data D2 of the same content as the first data D1 to the receiving apparatus in accordance with the second clock CK2 used in the receiving apparatus, 103 denotes a phase detector which inputs and compares the phases of the first clock CK1 and the second clock CK2 and determines whether the phase difference between the two clocks is within a predetermined value, and 104 denotes a phase controller which controls the timing for punching the first data D1 which is input in accordance with the second clock CK2 either directly or inverted based on the detection result of the phase detector 103.
In the phase matching circuit shown in FIG. 1, the first data D1 is taken by the first clock CK1 from the transmitting apparatus. The phase detector 103 receives the first clock CK1 and the second clock CK2 and detects whether a phase difference is within the predetermined value or not. Detection of the phase difference is necessary because if the first clock CK1 and the second clock CK2 have the same phase, then there is a high probability that when data is taken the content of receiving data will be changing in the receiving apparatus. Thus, accurate data reading is not possible. Therefore, when two clocks come close to the same phase, this problem occurs. This problem has been solved by shifting the phase of the first data D1 with a phase matching circuit.
The phase controller 104, which consists of an intermediate buffer 105 and a clock switch 106, receives the second clock CK2 and either inverts the second clock CK2 or uses it directly, depending on whether the phase difference between the first clock CK1 and the second clock CK2 is within the predetermined value or not. That is, the clock switch 106 causes data to be read from the intermediate buffer 105 with a clock, which is either the second clock CK2 directly or the second clock CK2 inverted depending on the phase difference detected by the phase detector 103. When the second clock CK2 is inverted due to such phase shift control, the inverted second clock is thereafter inverted again or normalized to the second clock CK2 when the phase difference is no longer within the predetermined value. As a result, phase shift control is carried out for the data being transmitted. However, the phase matching circuit associated with the prior art discussed above results in the following problems.
FIGS. 2A-2F and FIGS. 3A-3F illustrate timing charts for the phase matching circuit associated with the prior art. Designations A-F shown in FIG. 1 correspond to the timing charts of FIGS. 2A-2F and of FIGS. 3A-3F, respectively. FIGS. 2A-2F indicate that when the phase detector 103 detects the phase difference to be within the predetermined value, the phase of the second clock CK2 is shifted by inverting the second clock CK2 in the clock switch 106. FIGS. 3A-3F indicate that when the phase difference exceeds the predetermined value after being within the predetermined value, the inverted second clock is inverted again or normalized to the normal phase of the second clock CK2 in the clock switch 106. These phase shift operations cause the phase of the data to shift. A problem of such phase shift control, however, is that data are missed or read twice, as shown in FIGS. 2F and 3F. That is, the phase matching circuit associated with the prior art carries out phase shift control without relation to the content of the data. As a result, the above-mentioned problem arises in that the valid data to be read in the receiving side is missed or read twice. Thus, accurate processing cannot be conducted in the receiving side.